A computer system includes a set of interconnected components or modules of three basic types: central processing unit (CPU), memory, and input/output (I/O). The modules of the computer system are connected together by communication pathways known as busses. A bus is a shared transmission medium in that plural computer modules can transmit across the same bus. However, if two modules transmit during the same time period, their signals will overlap and become garbled. Therefore, it is important to ensure that only one module transmits across the bus during a given time period.
The process of allocating time or bandwidth on a computer bus among plural bus agents is known as arbitration. Typically, an arbiter grants access for a predetermined time period or bandwidth window to whichever bus agent first requests use of the bus. If plural bus agents have requests for use of the bus pending, then the arbiter typically employs a rotational priority or round-robin scheme to share the bus among the bus agents. In a rotational priority scheme, the use of the bus is given for one bandwidth window to each bus agent in sequential order. After the last bus agent uses the bus, then the use of the bus is given back to the first bus agent and the rotational sequence continues.
In many computer systems, such as the Intel P6 computer system, the bus agents can be either symmetric bus agents or priority bus agents. As the name suggests, bus requests from the priority bus agents have preference over any new bus requests from the symmetric bus agents. In the Intel P6 computer system, from one to four P6 processors are coupled to a processor bus, with each P6 processor being a symmetric bus agent. In addition, one or more bus controllers couple memory and input/output (I/O) devices to the processor bus, with each bus controller being a priority bus agent. The P6 processors are referred to as symmetric bus agents because they are arbitrated on a strict rotational priority scheme.
The prior art computer system 10 shown in FIG. 1 includes a multiprocessor system architecture in which first through fourth computer processors 14, 16, 18, 20 are each coupled to a processor bus 12. The computer processors 14-20 are known as symmetric bus agents, as discussed above. The computer system 10 also includes two priority bus agents: a bus agent 22 and a bus controller 24. Coupled to the bus agent 22 is a Peripheral Component Interconnect (PCI) bus 26 which is coupled to a hard drive 28 and a video controller 30. Coupled to the bus controller 24 is a main memory 32. The hard drive 28, video controller 30, and main memory 32 are bus requesters that generate bus requests for use of the processor bus 12.
The bus controller 24 includes an external arbiter 34 that arbitrates between requests for access to the processor bus 12. Such bus requests can come from the main memory 32 directly to the bus controller 24 or from the hard drive 28 and the video controller 30 to the bus agent 22 via the PCI bus 26. In response to receiving a bus request from the PCI bus 26, the bus agent 22 transmits an I/O request signal to the bus controller 24. The external arbiter 34 of the bus controller 24 performs arbitration between the I/O request signal from the bus agent 22 and any other bus requests, such as from the main memory 32. If the external arbiter 34 selects the I/O request signal from the bus agent 22, then the external arbiter transmits an I/O grant signal to the bus agent 22. Upon receiving the I/O grant signal, the bus agent 22 monitors a priority bus request line (BPRI#) of the processor bus 12 to determine whether the processor bus is available. If the BPRI# line is inactive when the I/O grant signal is received from the bus controller 24, then the bus agent activates the BPRI# line. When the BPRI# line is activated the bus agent 22 can transmit on the processor bus 12 a bus transaction (e.g., read or write) corresponding to the selected bus request from the PCI bus 26. An active BPRI# line informs the symmetric bus agents (i.e., processors 14-20) that they cannot transmit any bus transactions on the processor bus 12 until the BPRI# line is deactivated.
When the bus agent 22 is ready to finish transmitting transactions on the processor bus 12, the bus agent releases the I/O request signal and the BPRI# line to enable another bus agent to access the processor bus 12. For example, if the bus controller 24 is ready to transmit a transaction corresponding to a bus request received from the main memory 32, then the bus controller determines whether the BPRI# line is active. If the BPRI# line is not active, then the bus controller 24 activates the BPRI# line and transmits its transaction on the processor bus 12. As such, when switching between priority bus agents that are accessing the processor bus 12, the prior art system requires the first priority bus agent to deactivate the BPRI# line and the second priority bus agent must check to see if the BPRI# line is inactive, and then activate the BPRI# line.